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comparison intercom/g726/makefile.tcc @ 2:13be24d74cd2

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import intercom-0.4.1
author Peter Meerwald <pmeerw@cosy.sbg.ac.at>
date Fri, 25 Jun 2010 09:57:52 +0200
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1:9cadc470e3da 2:13be24d74cd2
1 # -----------------------------------------------------------------------------
2 # Borland tcc/bcc makefile for compiling and testing the G.726
3 # implementation. The executable must be defined by variable G726 below.
4 # 01.May.94 - Implemented by <simao@cpqd.ansp.br>
5 # 10.Mar.95 - Compilation and test sequence processing/comparison for
6 # vbr-g726.c. <simao@ctd.comsat.com>
7 # NOTE: you need to get (purchase) the G.726 test vectors from the ITU in
8 # order to perform the (optional) compliance test.
9 # -----------------------------------------------------------------------------
10
11 # ------------------------------------------------
12 # Choose compiler/options.
13 # ------------------------------------------------
14 #CC = bcc
15 CC = tcc
16 CC_OPT = -I../utl
17
18 # ------------------------------------------------
19 # General purpose symbols
20 # ------------------------------------------------
21 G726 = g726demo
22 VBR = vbr-g726 -q
23 DIFF = cf -q
24 RM = -rm -f
25
26 # ------------------------------------------------
27 # Choose an archiving utility:
28 # - public domain unzip, or [PC/Unix/VMS]
29 # - shareware pkunzip [PC only]
30 # ------------------------------------------------
31 #UNZIP = pkunzip
32 UNZIP = unzip -o
33
34 # ------------------------------------------------
35 # File lists
36 # ------------------------------------------------
37 TEST_VECTORS = *.?16 *.?24 *.?32 *.?40 *.rec
38
39 DEMO_OBJ = g726demo.obj g726.obj
40 VBR_OBJ = vbr-g726.obj g726.obj g711.obj
41
42 # ------------------------------------------------
43 # Targets
44 # ------------------------------------------------
45 all: g726demo vbr-g726
46
47 anyway: clean all
48
49 clean:
50 $(RM) *.obj
51
52 cleantest:
53 $(RM) $(TEST_VECTORS) voicvbra.tst voicvbru.tst voicvbrl.tst
54 $(RM) voice.src voicevbr.arf voicevbr.lrf voicevbr.urf
55
56 veryclean: clean cleantest
57 $(RM) g726demo.exe vbr-g726.exe
58
59 # -----------------------------------------------------------------------------
60 # Generic rules
61 # -----------------------------------------------------------------------------
62 .c.obj:
63 $(CC) $(CC_OPT) -c $<
64
65 # -----------------------------------------------------------------------------
66 # Specific rules
67 # -----------------------------------------------------------------------------
68 vbr-g726: vbr-g726.exe
69 g726demo: g726demo.exe
70
71 vbr-g726.exe: $(VBR_OBJ)
72 $(CC) -evbr-g726 $(VBR_OBJ)
73
74 g726demo.exe: $(DEMO_OBJ)
75 $(CC) -eg726demo $(DEMO_OBJ)
76
77 g726demo.obj: g726demo.c g726.h
78 $(CC) $(CC_OPT) -c -I../g711 g726demo.c
79
80 g726.obj: g726.c g726.h
81 $(CC) -c $(CC_OPT) g726.c
82
83 g711.obj: ../g711/g711.c
84 $(CC) -c $(CC_OPT) -I../g711 ../g711/g711.c
85
86 vbr-g726.obj: vbr-g726.c
87 $(CC) -c $(CC_OPT) -I../g711 vbr-g726.c
88
89 # ----------------------------------------
90 # Very simple portability test
91 # ----------------------------------------
92 test: test-vbr-quick
93 proc: proc-vbr-quick
94 comp: comp-vbr-quick
95
96 test-vbr-quick: proc-vbr-quick comp-vbr-quick
97 proc-vbr-quick: voice.src
98 $(VBR) -q -law A -rate 16-24-32-40-32-24 voice.src voicvbra.tst
99 $(VBR) -q -law l -rate 16-24-32-40-32-24 voice.src voicvbrl.tst
100 $(VBR) -q -law u -rate 16-24-32-40-32-24 voice.src voicvbru.tst
101 comp-vbr-quick: voicevbr.arf
102 $(DIFF) voicvbra.tst voicevbr.arf
103 $(DIFF) voicvbrl.tst voicevbr.lrf
104 $(DIFF) voicvbru.tst voicevbr.urf
105
106 voice.src: tst-g726.zip
107 $(UNZIP) tst-g726.zip voice.src
108 sb -over voice.src
109
110 voicevbr.arf: tst-g726.zip
111 $(UNZIP) tst-g726.zip voicevbr.arf voicevbr.lrf voicevbr.urf
112 swapover voicevbr.arf voicevbr.lrf voicevbr.urf
113
114 # -----------------------------------------------------------------------------
115 # Test the implementation for g726demo (compliance)
116 # In the automatic compliance testing, g726demo.c is verified by test-tv
117 # For vbr-g726.c, no differences should be observed, since both use g726.c,
118 # and differ only on the demo logic. For full compliance testing of the
119 # vbr-g726.c program, use test-tv-vbr
120 # -----------------------------------------------------------------------------
121 test-tv: proc-tv-fix comp-tv
122 proc-tv-fix: bin/rn16fa.o clean proc16-fix proc24-fix proc32-fix proc40-fix
123 comp-tv-fix: comp-tv
124 comp-tv: comp16 comp24 comp32 comp40
125
126 proc16-fix:
127 #
128 # Process ADPCM/ Coder for normal and overload sequences, A law
129 #
130 $(G726) a load 16 bin/nrm.a nrm.a16 256 1 64
131 $(G726) a load 16 bin/ovr.a ovr.a16 256 1 8
132 #
133 # Process ADPCM/ Decoder for normal and overload sequences, A law
134 #
135 $(G726) a adlo 16 bin/rn16fa.i rn16fa.rec 256 1 64
136 $(G726) a adlo 16 bin/rv16fa.i rv16fa.rec 256 1 8
137 #
138 # Process ADPCM/ Cross-decoder for normal and overload sequences,
139 # A law input -> ADPCM 16kbit/s -> mu law output
140 #
141 $(G726) u adlo 16 bin/rn16fa.i rn16fx.rec 256 1 64
142 $(G726) u adlo 16 bin/rv16fa.i rv16fx.rec 256 1 8
143 #
144 #
145 # Process ADPCM/ Coder for normal and overload sequences, mu law
146 #
147 $(G726) u load 16 bin/nrm.m nrm.m16 256 1 64
148 $(G726) u load 16 bin/ovr.m ovr.m16 256 1 8
149 #
150 # Process ADPCM/ Decoder for normal and overload sequences, mu law
151 #
152 $(G726) u adlo 16 bin/rn16fm.i rn16fm.rec 256 1 64
153 $(G726) u adlo 16 bin/rv16fm.i rv16fm.rec 256 1 8
154 #
155 # Process ADPCM/ Cross-decoder for normal and overload sequences,
156 # mu law input -> ADPCM 16kbit/s -> A law output
157 #
158 $(G726) a adlo 16 bin/rn16fm.i rn16fc.rec 256 1 64
159 $(G726) a adlo 16 bin/rv16fm.i rv16fc.rec 256 1 8
160 #
161 #
162 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
163 #
164 $(G726) a adlo 16 bin/i16 ri16fa.rec 256 1 64
165 $(G726) u adlo 16 bin/i16 ri16fm.rec 256 1 64
166
167 comp16:
168 #
169 # =================================================================
170 # COMPARISON OF FILES !
171 # =================================================================
172 #
173 # Compare ADPCM/ Coder for normal and overload sequences, A law
174 #
175 $(DIFF) bin/rn16fa.i nrm.a16 256 1 64
176 $(DIFF) bin/rv16fa.i ovr.a16 256 1 8
177 #
178 # Compare ADPCM/ Decoder for normal and overload sequences, A law
179 #
180 $(DIFF) bin/rn16fa.o rn16fa.rec 256 1 64
181 $(DIFF) bin/rv16fa.o rv16fa.rec 256 1 8
182 #
183 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
184 # A law input -> ADPCM x kbit/s -> mu law output
185 #
186 $(DIFF) bin/rn16fx.o rn16fx.rec 256 1 64
187 $(DIFF) bin/rv16fx.o rv16fx.rec 256 1 8
188 #
189 #
190 # Compare ADPCM/ Coder for normal and overload sequences, mu law
191 #
192 $(DIFF) bin/rn16fm.i nrm.m16 256 1 64
193 $(DIFF) bin/rv16fm.i ovr.m16 256 1 8
194 #
195 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
196 #
197 $(DIFF) bin/rn16fm.o rn16fm.rec 256 1 64
198 $(DIFF) bin/rv16fm.o rv16fm.rec 256 1 8
199 #
200 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
201 # mu law input -> ADPCM x kbit/s -> A law output
202 #
203 $(DIFF) bin/rn16fc.o rn16fc.rec 256 1 64
204 $(DIFF) bin/rv16fc.o rv16fc.rec 256 1 8
205 #
206 #
207 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
208 #
209 $(DIFF) bin/ri16fa.o ri16fa.rec 256 1 64
210 $(DIFF) bin/ri16fm.o ri16fm.rec 256 1 64
211
212 proc24-fix:
213 #
214 #
215 # Process ADPCM/ Coder for normal and overload sequences, A law
216 #
217 $(G726) a load 24 bin/nrm.a nrm.a24 256 1 64
218 $(G726) a load 24 bin/ovr.a ovr.a24 256 1 8
219 #
220 # Process ADPCM/ Decoder for normal and overload sequences, A law
221 #
222 $(G726) a adlo 24 bin/rn24fa.i rn24fa.rec 256 1 64
223 $(G726) a adlo 24 bin/rv24fa.i rv24fa.rec 256 1 8
224 #
225 # Process ADPCM/ Cross-decoder for normal and overload sequences,
226 # A law input -> ADPCM 24kbit/s -> mu law output
227 #
228 $(G726) u adlo 24 bin/rn24fa.i rn24fx.rec 256 1 64
229 $(G726) u adlo 24 bin/rv24fa.i rv24fx.rec 256 1 8
230 #
231 #
232 # Process ADPCM/ Coder for normal and overload sequences, mu law
233 #
234 $(G726) u load 24 bin/nrm.m nrm.m24 256 1 64
235 $(G726) u load 24 bin/ovr.m ovr.m24 256 1 8
236 #
237 # Process ADPCM/ Decoder for normal and overload sequences, mu law
238 #
239 $(G726) u adlo 24 bin/rn24fm.i rn24fm.rec 256 1 64
240 $(G726) u adlo 24 bin/rv24fm.i rv24fm.rec 256 1 8
241 #
242 # Process ADPCM/ Cross-decoder for normal and overload sequences,
243 # mu law input -> ADPCM 24kbit/s -> A law output
244 #
245 $(G726) a adlo 24 bin/rn24fm.i rn24fc.rec 256 1 64
246 $(G726) a adlo 24 bin/rv24fm.i rv24fc.rec 256 1 8
247 #
248 #
249 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
250 #
251 $(G726) a adlo 24 bin/i24 ri24fa.rec 256 1 64
252 $(G726) u adlo 24 bin/i24 ri24fm.rec 256 1 64
253
254 comp24:
255 #
256 # =================================================================
257 # COMPARISON OF FILES !
258 # =================================================================
259 #
260 # Compare ADPCM/ Coder for normal and overload sequences, A law
261 #
262 $(DIFF) bin/rn24fa.i nrm.a24 256 1 64
263 $(DIFF) bin/rv24fa.i ovr.a24 256 1 8
264 #
265 # Compare ADPCM/ Decoder for normal and overload sequences, A law
266 #
267 $(DIFF) bin/rn24fa.o rn24fa.rec 256 1 64
268 $(DIFF) bin/rv24fa.o rv24fa.rec 256 1 8
269 #
270 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
271 # A law input -> ADPCM x kbit/s -> mu law output
272 #
273 $(DIFF) bin/rn24fx.o rn24fx.rec 256 1 64
274 $(DIFF) bin/rv24fx.o rv24fx.rec 256 1 8
275 #
276 #
277 # Compare ADPCM/ Coder for normal and overload sequences, mu law
278 #
279 $(DIFF) bin/rn24fm.i nrm.m24 256 1 64
280 $(DIFF) bin/rv24fm.i ovr.m24 256 1 8
281 #
282 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
283 #
284 $(DIFF) bin/rn24fm.o rn24fm.rec 256 1 64
285 $(DIFF) bin/rv24fm.o rv24fm.rec 256 1 8
286 #
287 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
288 # mu law input -> ADPCM x kbit/s -> A law output
289 #
290 $(DIFF) bin/rn24fc.o rn24fc.rec 256 1 64
291 $(DIFF) bin/rv24fc.o rv24fc.rec 256 1 8
292 #
293 #
294 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
295 #
296 $(DIFF) bin/ri24fa.o ri24fa.rec 256 1 64
297 $(DIFF) bin/ri24fm.o ri24fm.rec 256 1 64
298
299 proc32-fix:
300 #
301 # Process ADPCM/ Coder for normal and overload sequences, A law
302 #
303 $(G726) a load 32 bin/nrm.a nrm.a32 256 1 64
304 $(G726) a load 32 bin/ovr.a ovr.a32 256 1 8
305 #
306 # Process ADPCM/ Decoder for normal and overload sequences, A law
307 #
308 $(G726) a adlo 32 bin/rn32fa.i rn32fa.rec 256 1 64
309 $(G726) a adlo 32 bin/rv32fa.i rv32fa.rec 256 1 8
310 #
311 # Process ADPCM/ Cross-decoder for normal and overload sequences,
312 # A law input -> ADPCM 32kbit/s -> mu law output
313 #
314 $(G726) u adlo 32 bin/rn32fa.i rn32fx.rec 256 1 64
315 $(G726) u adlo 32 bin/rv32fa.i rv32fx.rec 256 1 8
316 #
317 #
318 # Process ADPCM/ Coder for normal and overload sequences, mu law
319 #
320 $(G726) u load 32 bin/nrm.m nrm.m32 256 1 64
321 $(G726) u load 32 bin/ovr.m ovr.m32 256 1 8
322 #
323 # Process ADPCM/ Decoder for normal and overload sequences, mu law
324 #
325 $(G726) u adlo 32 bin/rn32fm.i rn32fm.rec 256 1 64
326 $(G726) u adlo 32 bin/rv32fm.i rv32fm.rec 256 1 8
327 #
328 # Process ADPCM/ Cross-decoder for normal and overload sequences,
329 # mu law input -> ADPCM 32kbit/s -> A law output
330 #
331 $(G726) a adlo 32 bin/rn32fm.i rn32fc.rec 256 1 64
332 $(G726) a adlo 32 bin/rv32fm.i rv32fc.rec 256 1 8
333 #
334 #
335 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
336 #
337 $(G726) a adlo 32 bin/i32 ri32fa.rec 256 1 64
338 $(G726) u adlo 32 bin/i32 ri32fm.rec 256 1 64
339
340 comp32:
341 #
342 # =================================================================
343 # COMPARISON OF FILES !
344 # =================================================================
345 #
346 # Compare ADPCM/ Coder for normal and overload sequences, A law
347 #
348 $(DIFF) bin/rn32fa.i nrm.a32 256 1 64
349 $(DIFF) bin/rv32fa.i ovr.a32 256 1 8
350 #
351 # Compare ADPCM/ Decoder for normal and overload sequences, A law
352 #
353 $(DIFF) bin/rn32fa.o rn32fa.rec 256 1 64
354 $(DIFF) bin/rv32fa.o rv32fa.rec 256 1 8
355 #
356 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
357 # A law input -> ADPCM x kbit/s -> mu law output
358 #
359 $(DIFF) bin/rn32fx.o rn32fx.rec 256 1 64
360 $(DIFF) bin/rv32fx.o rv32fx.rec 256 1 8
361 #
362 #
363 # Compare ADPCM/ Coder for normal and overload sequences, mu law
364 #
365 $(DIFF) bin/rn32fm.i nrm.m32 256 1 64
366 $(DIFF) bin/rv32fm.i ovr.m32 256 1 8
367 #
368 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
369 #
370 $(DIFF) bin/rn32fm.o rn32fm.rec 256 1 64
371 $(DIFF) bin/rv32fm.o rv32fm.rec 256 1 8
372 #
373 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
374 # mu law input -> ADPCM x kbit/s -> A law output
375 #
376 $(DIFF) bin/rn32fc.o rn32fc.rec 256 1 64
377 $(DIFF) bin/rv32fc.o rv32fc.rec 256 1 8
378 #
379 #
380 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
381 #
382 $(DIFF) bin/ri32fa.o ri32fa.rec 256 1 64
383 $(DIFF) bin/ri32fm.o ri32fm.rec 256 1 64
384
385 proc40-fix:
386 #
387 #
388 # Process ADPCM/ Coder for normal and overload sequences, A law
389 #
390 $(G726) a load 40 bin/nrm.a nrm.a40 256 1 64
391 $(G726) a load 40 bin/ovr.a ovr.a40 256 1 8
392 #
393 # Process ADPCM/ Decoder for normal and overload sequences, A law
394 #
395 $(G726) a adlo 40 bin/rn40fa.i rn40fa.rec 256 1 64
396 $(G726) a adlo 40 bin/rv40fa.i rv40fa.rec 256 1 8
397 #
398 # Process ADPCM/ Cross-decoder for normal and overload sequences,
399 # A law input -> ADPCM 40kbit/s -> mu law output
400 #
401 $(G726) u adlo 40 bin/rn40fa.i rn40fx.rec 256 1 64
402 $(G726) u adlo 40 bin/rv40fa.i rv40fx.rec 256 1 8
403 #
404 #
405 # Process ADPCM/ Coder for normal and overload sequences, mu law
406 #
407 $(G726) u load 40 bin/nrm.m nrm.m40 256 1 64
408 $(G726) u load 40 bin/ovr.m ovr.m40 256 1 8
409 #
410 # Process ADPCM/ Decoder for normal and overload sequences, mu law
411 #
412 $(G726) u adlo 40 bin/rn40fm.i rn40fm.rec 256 1 64
413 $(G726) u adlo 40 bin/rv40fm.i rv40fm.rec 256 1 8
414 #
415 # Process ADPCM/ Cross-decoder for normal and overload sequences,
416 # mu law input -> ADPCM 40kbit/s -> A law output
417 #
418 $(G726) a adlo 40 bin/rn40fm.i rn40fc.rec 256 1 64
419 $(G726) a adlo 40 bin/rv40fm.i rv40fc.rec 256 1 8
420 #
421 #
422 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
423 #
424 $(G726) a adlo 40 bin/i40 ri40fa.rec 256 1 64
425 $(G726) u adlo 40 bin/i40 ri40fm.rec 256 1 64
426
427 comp40:
428 #
429 # =================================================================
430 # COMPARISON OF FILES !
431 # =================================================================
432 #
433 # Compare ADPCM/ Coder for normal and overload sequences, A law
434 #
435 $(DIFF) bin/rn40fa.i nrm.a40 256 1 64
436 $(DIFF) bin/rv40fa.i ovr.a40 256 1 8
437 #
438 # Compare ADPCM/ Decoder for normal and overload sequences, A law
439 #
440 $(DIFF) bin/rn40fa.o rn40fa.rec 256 1 64
441 $(DIFF) bin/rv40fa.o rv40fa.rec 256 1 8
442 #
443 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
444 # A law input -> ADPCM x kbit/s -> mu law output
445 #
446 $(DIFF) bin/rn40fx.o rn40fx.rec 256 1 64
447 $(DIFF) bin/rv40fx.o rv40fx.rec 256 1 8
448 #
449 #
450 # Compare ADPCM/ Coder for normal and overload sequences, mu law
451 #
452 $(DIFF) bin/rn40fm.i nrm.m40 256 1 64
453 $(DIFF) bin/rv40fm.i ovr.m40 256 1 8
454 #
455 # Compare ADPCM/ Decoder for normal and overload sequences, mu law
456 #
457 $(DIFF) bin/rn40fm.o rn40fm.rec 256 1 64
458 $(DIFF) bin/rv40fm.o rv40fm.rec 256 1 8
459 #
460 # Compare ADPCM/ Cross-decoder for normal and overload sequences,
461 # mu law input -> ADPCM x kbit/s -> A law output
462 #
463 $(DIFF) bin/rn40fc.o rn40fc.rec 256 1 64
464 $(DIFF) bin/rv40fc.o rv40fc.rec 256 1 8
465 #
466 #
467 # Compare ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
468 #
469 $(DIFF) bin/ri40fa.o ri40fa.rec 256 1 64
470 $(DIFF) bin/ri40fm.o ri40fm.rec 256 1 64
471
472
473 # -----------------------------------------------------------------------------
474 # Test the implementation for vbr-g726 (compliance)
475 # -----------------------------------------------------------------------------
476 test-vbr-tv: proc-vbr-tv comp-tv
477 proc-vbr-tv: bin/rn16fa.o clean proc16-vbr proc24-vbr proc32-vbr proc40-vbr
478 comp-vbr-tv: comp-tv
479
480 proc16-vbr:
481 # Process ADPCM/ Coder for normal and overload sequences, A law
482 $(VBR) -law a -enc -rate 16 bin/nrm.a nrm.a16 16 1 1024
483 $(VBR) -law a -enc -rate 16 bin/ovr.a ovr.a16 16 1 128
484 # Process ADPCM/ Decoder for normal and overload sequences, A law
485 $(VBR) -law a -dec -rate 16 bin/rn16fa.i rn16fa.rec 16 1 1024
486 $(VBR) -law a -dec -rate 16 bin/rv16fa.i rv16fa.rec 16 1 128
487 # Process ADPCM/ Cross-decoder for normal and overload sequences,
488 # A law input -> ADPCM 16kbit/s -> mu law output
489 $(VBR) -law u -dec -rate 16 bin/rn16fa.i rn16fx.rec 16 1 1024
490 $(VBR) -law u -dec -rate 16 bin/rv16fa.i rv16fx.rec 16 1 128
491 # Process ADPCM/ Coder for normal and overload sequences, mu law
492 $(VBR) -law u -enc -rate 16 bin/nrm.m nrm.m16 16 1 1024
493 $(VBR) -law u -enc -rate 16 bin/ovr.m ovr.m16 16 1 128
494 # Process ADPCM/ Decoder for normal and overload sequences, mu law
495 $(VBR) -law u -dec -rate 16 bin/rn16fm.i rn16fm.rec 16 1 1024
496 $(VBR) -law u -dec -rate 16 bin/rv16fm.i rv16fm.rec 16 1 128
497 # Process ADPCM/ Cross-decoder for normal and overload sequences,
498 # mu law input -> ADPCM 16kbit/s ->A law output
499 $(VBR) -law a -dec -rate 16 bin/rn16fm.i rn16fc.rec 16 1 1024
500 $(VBR) -law a -dec -rate 16 bin/rv16fm.i rv16fc.rec 16 1 128
501 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
502 $(VBR) -law a -dec -rate 16 bin/i16 ri16fa.rec 16 1 1024
503 $(VBR) -law u -dec -rate 16 bin/i16 ri16fm.rec 16 1 1024
504
505 proc24-vbr:
506 # Process ADPCM/ Coder for normal and overload sequences, A law
507 $(VBR) -law a -enc -rate 24 bin/nrm.a nrm.a24 16 1 1024
508 $(VBR) -law a -enc -rate 24 bin/ovr.a ovr.a24 16 1 128
509 # Process ADPCM/ Decoder for normal and overload sequences, A law
510 $(VBR) -law a -dec -rate 24 bin/rn24fa.i rn24fa.rec 16 1 1024
511 $(VBR) -law a -dec -rate 24 bin/rv24fa.i rv24fa.rec 16 1 128
512 # Process ADPCM/ Cross-decoder for normal and overload sequences,
513 # A law input -> ADPCM 24kbit/s -> mu law output
514 $(VBR) -law u -dec -rate 24 bin/rn24fa.i rn24fx.rec 16 1 1024
515 $(VBR) -law u -dec -rate 24 bin/rv24fa.i rv24fx.rec 16 1 128
516 # Process ADPCM/ Coder for normal and overload sequences, mu law
517 $(VBR) -law u -enc -rate 24 bin/nrm.m nrm.m24 16 1 1024
518 $(VBR) -law u -enc -rate 24 bin/ovr.m ovr.m24 16 1 128
519 # Process ADPCM/ Decoder for normal and overload sequences, mu law
520 $(VBR) -law u -dec -rate 24 bin/rn24fm.i rn24fm.rec 16 1 1024
521 $(VBR) -law u -dec -rate 24 bin/rv24fm.i rv24fm.rec 16 1 128
522 # Process ADPCM/ Cross-decoder for normal and overload sequences,
523 # mu law input -> ADPCM 24kbit/s ->A law output
524 $(VBR) -law a -dec -rate 24 bin/rn24fm.i rn24fc.rec 16 1 1024
525 $(VBR) -law a -dec -rate 24 bin/rv24fm.i rv24fc.rec 16 1 128
526 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
527 $(VBR) -law a -dec -rate 24 bin/i24 ri24fa.rec 16 1 1024
528 $(VBR) -law u -dec -rate 24 bin/i24 ri24fm.rec 16 1 1024
529
530 proc32-vbr:
531 # Process ADPCM/ Coder for normal and overload sequences, A law
532 $(VBR) -law a -enc -rate 32 bin/nrm.a nrm.a32 16 1 1024
533 $(VBR) -law a -enc -rate 32 bin/ovr.a ovr.a32 16 1 128
534 # Process ADPCM/ Decoder for normal and overload sequences, A law
535 $(VBR) -law a -dec -rate 32 bin/rn32fa.i rn32fa.rec 16 1 1024
536 $(VBR) -law a -dec -rate 32 bin/rv32fa.i rv32fa.rec 16 1 128
537 # Process ADPCM/ Cross-decoder for normal and overload sequences,
538 # A law input -> ADPCM 32kbit/s -> mu law output
539 $(VBR) -law u -dec -rate 32 bin/rn32fa.i rn32fx.rec 16 1 1024
540 $(VBR) -law u -dec -rate 32 bin/rv32fa.i rv32fx.rec 16 1 128
541 # Process ADPCM/ Coder for normal and overload sequences, mu law
542 $(VBR) -law u -enc -rate 32 bin/nrm.m nrm.m32 16 1 1024
543 $(VBR) -law u -enc -rate 32 bin/ovr.m ovr.m32 16 1 128
544 # Process ADPCM/ Decoder for normal and overload sequences, mu law
545 $(VBR) -law u -dec -rate 32 bin/rn32fm.i rn32fm.rec 16 1 1024
546 $(VBR) -law u -dec -rate 32 bin/rv32fm.i rv32fm.rec 16 1 128
547 # Process ADPCM/ Cross-decoder for normal and overload sequences,
548 # mu law input -> ADPCM 32kbit/s ->A law output
549 $(VBR) -law a -dec -rate 32 bin/rn32fm.i rn32fc.rec 16 1 1024
550 $(VBR) -law a -dec -rate 32 bin/rv32fm.i rv32fc.rec 16 1 128
551 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
552 $(VBR) -law a -dec -rate 32 bin/i32 ri32fa.rec 16 1 1024
553 $(VBR) -law u -dec -rate 32 bin/i32 ri32fm.rec 16 1 1024
554
555 proc40-vbr:
556 # Process ADPCM/ Coder for normal and overload sequences, A law
557 $(VBR) -law a -enc -rate 40 bin/nrm.a nrm.a40 16 1 1024
558 $(VBR) -law a -enc -rate 40 bin/ovr.a ovr.a40 16 1 128
559 # Process ADPCM/ Decoder for normal and overload sequences, A law
560 $(VBR) -law a -dec -rate 40 bin/rn40fa.i rn40fa.rec 16 1 1024
561 $(VBR) -law a -dec -rate 40 bin/rv40fa.i rv40fa.rec 16 1 128
562 # Process ADPCM/ Cross-decoder for normal and overload sequences,
563 # A law input -> ADPCM 40kbit/s -> mu law output
564 $(VBR) -law u -dec -rate 40 bin/rn40fa.i rn40fx.rec 16 1 1024
565 $(VBR) -law u -dec -rate 40 bin/rv40fa.i rv40fx.rec 16 1 128
566 # Process ADPCM/ Coder for normal and overload sequences, mu law
567 $(VBR) -law u -enc -rate 40 bin/nrm.m nrm.m40 16 1 1024
568 $(VBR) -law u -enc -rate 40 bin/ovr.m ovr.m40 16 1 128
569 # Process ADPCM/ Decoder for normal and overload sequences, mu law
570 $(VBR) -law u -dec -rate 40 bin/rn40fm.i rn40fm.rec 16 1 1024
571 $(VBR) -law u -dec -rate 40 bin/rv40fm.i rv40fm.rec 16 1 128
572 # Process ADPCM/ Cross-decoder for normal and overload sequences,
573 # mu law input -> ADPCM 40kbit/s ->A law output
574 $(VBR) -law a -dec -rate 40 bin/rn40fm.i rn40fc.rec 16 1 1024
575 $(VBR) -law a -dec -rate 40 bin/rv40fm.i rv40fc.rec 16 1 128
576 # Process ADPCM/ Decode-only for the same input ADPCM sequence, A and mu law
577 $(VBR) -law a -dec -rate 40 bin/i40 ri40fa.rec 16 1 1024
578 $(VBR) -law u -dec -rate 40 bin/i40 ri40fm.rec 16 1 1024
579
580

Repositories maintained by Peter Meerwald, pmeerw@pmeerw.net.